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ATtiny261A Datasheet(PDF) 144 Page - ATMEL Corporation

Part # ATtiny261A
Description  8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
PDF  292 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATtiny261A Datasheet(HTML) 144 Page - ATMEL Corporation

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8197A–AVR–10/09
ATtiny261A/461A/861A
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low. See Figure 15-3.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,
as shown in Figure 15-4 below.
Figure 15-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. See Figure 15-5.
When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set.
In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC
again, and a new conversion will be initiated on the first rising ADC clock edge.
Figure 15-5. ADC Timing Diagram, Single Conversion
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1
212
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
1
2
3
4
5
6
7
8
9
10
11
12
13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion
Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update



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