AS3525 datasheet(110/194 Pages) AMSCO

110 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

110

- 194

Table 28 Processor USB Clock Controller Register

Name

Base

Default

CGU_USB

AS3525_CGU_BASE

0x00

USB Clock ControllerRegister

Offset0x1c

This register allows setting the USB PHY interface clock.

Bit

Bit Name

Default

Access

Bit Description

USB_CLK_EN

0x00

R/W

USB PHY clock enable => clk_usb

4:2

USB_DIV_SEL [2:0]

0x00

R/W

division ratio

0: div = 1/1

> 0: div = 1/(2*n); (even division factors only)

1:0

USB_SEL[1:0]

0x00

R/W

clkin select

00: clk_main

01: plla_fout

10: pllb_fout

11: reserved (clk_main)

Note:

The clock gating bit applies only to the USB PHY clock. To enable/disable the clock to the AHB part (USB CORE) CGU_PERI

has to be configured.

f(clk_usb) = f(clk_core_48m) = f(clkin) * div;

Table 29 Interrupt Mask and PLL Lock Status Register

Name

Base

Default

CGU_INTCTRL

AS3525_CGU_BASE

0x00

Interrupt Mask and PLL Lock Status Register

Offset: 0x20

Bit

Bit Name

Default

Access

Bit Description

INT_EN_PLLB_LOCK

0x00

R/W

interrupt on PLLB lock enable (R/W)

INT_EN_PLLA_LOCK

0x00

R/W

interrupt on PLLA lock enable (R/W)

PLLB_LOCK

0x00

PLLB lock status, locked if SET (not cleared on read)

PLLA_LOCK

PLLA lock status, locked if SET (not cleared on read)

Table 30 Interrupt Clear Register

Name

Base

Default

CGU_IRQ

AS3525_CGU_BASE

0x00

Interrupt Clear Register

Offset: 0x24

Bit

Bit Name

Default

Access

Bit Description

PLLB_LOCK

0x00

PLLB lock status, locked if SET (not cleared on read)

PLLA_LOCK

0x00

PLLA lock status, locked if SET (not cleared on read)

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