AS3525 datasheet(111/194 Pages) AMSCO

111 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

111

- 194

Table 31 PLL A Lock Counter Register

Name

Base

Default

CGU_COUNTA

AS3525_CGU_BASE

0x20

PLL A Lock Counter Register

Offset: 0x28

Bit

Bit Name

Default

Access

Bit Description

7:0

COUNTA[7:0]

0x00

R/W

number of PLL A’s fout-clock cycles until the LOCKA

bit is set

Table 32 PLL B Lock Counter Register

Name

Base

Default

CGU_COUNTB

AS3525_CGU_BASE

0x20

PLL B Lock Counter Register

Offset: 0x2c

Bit

Bit Name

Default

Access

Bit Description

7:0

COUNTB[7:0]

0x00

R/W

number of PLL B’s fout-clock cycles until the LOCKB

bit is set

Table 33 IDE Clock Controller Register

Name

Base

Default

CGU_IDE

AS3525_CGU_BASE

0x20

IDE Clock Controller Register

Offset: 0x30

This register allows setting the IDE interface clocks.

Bit

Bit Name

Default

Access

Bit Description

IDEIF_CLK_EN

R/W

IDE AHB IF clock enable

IDE_CLK_EN

R/W

IDE IF clock enable (90MHz domain) => clk_ide

5:2

IDE_DIV_SEL [2:0]

0x0

R/W

division ratio => div = 1/(ide_div_sel + 1)

1:0

IDE_SEL[1:0]

0x0

R/W

clkin select (clk_ide)

00: clk_main

01: plla_fout

10: pllb_fout

11: reserved (clk_main)

Note: f(clk_ide) := f(clkin) * div;

AS3525 Datasheet(PDF) 111 Page - ams AG

AS3525 Datasheet(HTML) 111 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL