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AS3525 Datasheet(PDF) 115 Page - ams AG

Part # AS3525
Description  Advanced Audio Processor System
PDF  194 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3525 Datasheet(HTML) 115 Page - ams AG

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AS3525-A/-B C22O22
Data Sheet, Confidential
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.13
115
- 194
Name
Base
Default
CCU_SRC
AS3525_CCU_BASE
0x00
Software Reset Control Register
Offset: 0x0000h
Writing a logic 1 to the single bits in the read/write register enables resets to each
module.
Bit
Bit Name
Default
Access
Bit Description
16
UART_EN
0
R/W
1: enable UART interface reset
0: disable UART interface reset
15
NAF_EN
0
R/W
1: enable NAND flash/Smart Media interface reset
0: disable NAND flash/Smart Media interface reset
14
SDMCI_EN
0
R/W
1: enable secure digital/multimedia interface reset
0: disable secure digital/multimedia interface reset
13
GPIO_EN
0
R/W
1: enable general purpose IO reset
0: disable general purpose IO reset
12
I2C_AUDIO_EN
0
R/W
1: enable audio I2C interface reset
0: disable audio I2C interface reset
11
I2C_EN
0
R/W
1: enable master/slave I2C interface reset
0: disable master/slave I2C interface reset
10
MMS_EN
0
R/W
1: enable memory stick interface reset
0: disable memory stick interface reset
9
I2SI_APB_EN
0
R/W
1: enable I2S input interface reset for APB part
0: disable I2S input interface reset for APB part
8
I2SO_APB_EN
0
R/W
1: enable I2S output interface reset for APB part
0: disable I2S output interface reset for APB part
7
USB_AHB_EN
0
R/W
1: enable USB AHB reset
0: disable USB AHB reset
6
USB_PHY_EN
0
R/W
1: enable USB PHY reset
0: disable USB PHY reset
5
DMAC_EN
0
R/W
1: enable DMA controller reset
0: disable DMA controller reset
4
VIC_EN
0
R/W
1: enable vectored interrupt cell reset
0: disable vectored interrupt cell reset
3
RAMC_EN
0
R/W
1: enable RAMC reset
0: disable RAMC reset
2
1TRAM_EN
0
R/W
1: enable 1TRAM reset
0: disable 1TRAM reset
1
MPMC_EN
0
R/W
1: enable external memory AHB reset
0: disable external memory AHB reset
0
BRIDGE_EN
0
R/W
1: enable bridge reset
0: disable bridge reset
Table 90 Software Reset Lock Register
Name
Base
Default
CCU_SRL
AS3525_CCU_BASE
0x00
Software Reset Lock Register
Offset: 0x0004h
Use of this register enables the software reset selected with Software Reset Control
Register. Writing a value of 0x1A720212 will enable the selected reset; writing any
other value will not enable software reset.
Bit
Bit Name
Default
Access
Bit Description
0:31
software_reset_lock
0
R/W
0x1A720212: enables selected reset
Other values: no effect



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