AS3525 datasheet(116/194 Pages) AMSCO

116 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

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Revision 1.13

116

- 194

7.3.15.2 IO_PADRING functions

Within the IO_PADRING module all multiplexing for selecting alternative functions is implemented. The selection of active functions is chosen within

the IO_configuration_register. Following table gives a description of the IO configurations:

Table 91 IO_PADRING Configurations

Name

Base

Default

CCU_IO

AS3525_CCU_BASE

0x00

IO Configuration Registers

Offset: 0x000Ch

With this read/write registers the functionality of IOs are controlled which provides

several different functions

Bit

Bit Name

Default

Access

Bit Description

8:7

naf_ce_sel[1:0]

R/W

these bits select which output is used for NAF ce_n.

0: naf_ce0_n

1: naf_ce1_n

2: naf_ce2_n

3: naf_ce3_n

pll_probe_en

R/W

test mode:

1: pll output clock is available at a GPIO Pin

ide_sel

R/W

1: the IDE input/output configuration is set

spi_flash_mode

R/W

SPI used in master mode:

1: pin SSP_FSSOUT always 0

0: pin SSP_FSSOUT generated by SSP hardware block

SPI used in slave mode:

spi_flash_mode hast to be switched to 0

3:2

xpd_func_sel(1:0)

R/W

00: XPD works as general purpose IO

01: SD-MCI interface

10: the XPD[5:0] are configured to support MS, XPD[7:6} are

general IO pins

11: reserved (XPD works as general IO)

i2c_ms_sel

R/W

1: the I2C master/slave IO configuration is set

uart_sel

R/W

1: the uart IO configuration is set

7.3.15.3 Other CCU functions

With the CCU_MEMMAP register, the remap(r/w) and int_boot_sel (read only) bits are accessible.

Table 92 Memory Map Register

Name

Base

Default

CCU_MEMMAP

AS3525_CCU_BASE

N/A

Memory Map Register

Offset: 0x0008h

With the register the remap(r/w) and int_boot_sel (r only) bits are accessible.

Bit

Bit Name

Default

Access

Bit Description

INT_BOOT_SEL

external

XPC[0]

Boot selection

1: internal ROM

0: external memory interface

REMAP

R/W

Defines memory mapping

1: RAM

0: ROM

If the INIT_BOOT_SEL is 0 (boot from external memory interface), following pins will be latched at startup to define the MPMC interface settings:

•

mpmc_stcs1mw[0]

•

mpmc_stcs1pb

•

mpmc_stcs1pol

•

mpmc_rel1config

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