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AS3525 Datasheet(PDF) 178 Page - ams AG |
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AS3525 Datasheet(HTML) 178 Page - ams AG |
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178 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 178 - 194 Ball Nr. BGA224 Ball Name PAD Type I/O Ball Description spdif_data_in I SPDIF data input data input for SPDIF to I2S conversion Audio Subsystem IRQ N1 INTRQ intrq DO D IN ST O I used by the audio/PMU subsystem to interrupt the digital core, INTRQ and intrq are connected on the BGA JTAG Debugging IF C2 jtag_trst_n D IN ST PD I JTAG reset not A1 jtag_tms D IN ST PU I JTAG mode select B2 jtag_tck D IN ST PU I JTAG clock B1 jtag_tdi D IN ST PU I JTAG data input D3 jtag_tdo D IO ST PU LSR O JTAG data output External Memory IF G5 mpmc_addr[0] D OUT LSR LV O EXT. MEMORY address line B5 mpmc_addr[1] D OUT LSR LV O EXT. MEMORY address line L4 mpmc_addr[2] D OUT LSR LV O EXT. MEMORY address line A5 mpmc_addr[3] D OUT LSR LV O EXT. MEMORY address line K5 mpmc_addr[4] D OUT LSR LV O EXT. MEMORY address line D6 mpmc_addr[5] D OUT LSR LV O EXT. MEMORY address line F6 mpmc_addr[6] D OUT LSR LV O EXT. MEMORY address line C6 mpmc_addr[7] D OUT LSR LV O EXT. MEMORY address line E6 mpmc_addr[8] D OUT LSR LV O EXT. MEMORY address line A6 mpmc_addr[9] D OUT LSR LV O EXT. MEMORY address line H5 mpmc_addr[10] D OUT LSR LV O EXT. MEMORY address line B6 mpmc_addr[11] D OUT LSR LV O EXT. MEMORY address line J5 mpmc_addr[12] D OUT LSR LV O EXT. MEMORY address line D7 mpmc_addr[13] D OUT LSR LV O EXT. MEMORY address line E7 mpmc_addr[14] D OUT LSR LV O EXT. MEMORY address line C7 mpmc_addr[15] D OUT LSR LV O EXT. MEMORY address line F7 mpmc_addr[16] D OUT LSR LV O EXT. MEMORY address line A7 mpmc_addr[17] D OUT LSR LV O EXT. MEMORY address line G6 mpmc_addr[18] D OUT LSR LV O EXT. MEMORY address line B7 mpmc_addr[19] D OUT LSR LV O EXT. MEMORY address line H6 mpmc_addr[20] D OUT LSR LV O EXT. MEMORY address line F8 mpmc_cke[0] D OUT LSR LV O EXT. MEMORY clock enable0 used for SDRAM devices only J6 mpmc_cke[1] D OUT LSR LV O EXT. MEMORY clock enable 1 used for SDRAM devices only E8 mpmc_clk[0] D OUT LSR LV O EXT. MEMORY clock 0 used for SDRAM devices only G7 mpmc_clk[1] D OUT LSR LV O EXT. MEMORY clock 1 used for SDRAM devices only L5 mpmc_fbclkin D IO ST PD LSR LV O EXT. MEMORY feedback clock used for SDRAM devices only D8 mpmc_dqm[0] D OUT LSR LV O EXT. MEMORY data mask 0 used for SDRAM devices and static memories L6 mpmc_dqm[1] D OUT LSR LV O EXT. MEMORY data mask 1 used for SDRAM devices and static memories A8 mpmc_cas_n D OUT LSR LV O EXT. MEMORY column address strobe not used for SDRAM devices only K6 mpmc_dycs_n[0] D OUT LSR LV O EXT. MEMORY dynamic memory chip select 0 not |
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