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AS3525 Datasheet(PDF) 177 Page - ams AG |
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AS3525 Datasheet(HTML) 177 Page - ams AG |
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177 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 177 - 194 Ball Nr. BGA224 Ball Name PAD Type I/O Ball Description naf_ce0_n O NAND FLASH chip enable E15 ide_cs0_n D IO ST LSR O IDE chip select 0 used by the host to select command block registers in the device naf_ce1_n O NAND FLASH chip enable H11 ide_cs1_n D IO ST LSR O IDE chip select 1 used by the host to select control block registers in the device naf_ce2_n O NAND FLASH chip enable J11 ide_hiown D IO ST LSR O IDE host IO write strobe naf_ce3_n O NAND FLASH chip enable G13 ide_hiorn D IO ST LSR O IDE host IO read strobe naf_we_n O NAND FLASH write enable not G14 ide_dackn D IO ST LSR O IDE DMA acknowledge used by the host to initiate DMA data transfers naf_re_n O NAND FLASH read enable not H12 ide_npcblid D IO ST LSR I IDE primary channel cable ID detect naf_bsy_n I NAND FLASH ready / busy not F15 ide_nscblid D IO ST LSR I IDE secondary channel cable ID select A12 ide_ha[0] D OUT LSR O IDE host address H10 ide_ha[1] D OUT LSR O IDE host address D12 ide_ha[2] D OUT LSR O IDE host address G10 ide_reset_n D OUT LSR O IDE reset not, used by the host to reset the device I2S Output M6 i2so_sdata SDI D OUT LSR DI O I IS2 data output data output from digital core to audio sub system, SDI and i2so_sdata are connected on the BGA N6 i2so_sclk SCLK D OUT LSR DI O I I2S serial clock clock output from digital core to audio sub system, SCLK and isoi_sclk are connected on the BGA N5 i2so_lrck LRCK D OUT LSR DI O I I2S left/right clock clock output from digital core to audio sub system, LRCK and i2so_lrck are connected on the BGA M5 i2so_mclk MCLK D OUT LSR DI O I I2S master clock clock output from digital core to audio sub system, MCLK and i2so_mclk are connected on the BGA I2S Input M7 i2si_sdata SDO D IN ST DO I O I2S data input data output from audio sub system to digital core, SDO and i2si_sdata are connected on the BGA i2si_sclk_out O I2S master serial clock serial clock output for external ADC if AS3525 is I2S master E3 i2si_sclk_in D IO ST LSR I I2S slave serial clock serial clock input for external ADC if AS3525 is I2S slave i2si_lrck_out O I2S master, left/right clock left/right clock output for external ADC if AS3525 is I2S master D1 i2si_lrck_in D IO ST LSR I I2S slave, left/right clock left/right clock input for external ADC if AS3525 is I2S master E4 i2si_mclk D OUT LSR O I2S master, master clock C1 i2si_sdata_in D IN ST PD I I2S data input data input from external audio ADC |
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