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AS3525 Datasheet(PDF) 174 Page - ams AG

Part # AS3525
Description  Advanced Audio Processor System
PDF  194 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3525 Datasheet(HTML) 174 Page - ams AG

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AS3525-A/-B C22O22
Data Sheet, Confidential
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.13
174
- 194
Ball Nr.
BGA224
Ball Name
PAD Type
I/O
Ball Description
Port A
B4
xpa[0]
D IO ST PD LSR
IO GPIO IO, Port A
G4
xpa[1]
D IO ST PD LSR
IO GPIO IO, Port A
A4
xpa[2]
D IO ST PD LSR
IO GPIO IO, Port A
H4
xpa[3]
D IO ST PD LSR
IO GPIO IO, Port A
D5
xpa[4]
D IO ST PD LSR
IO GPIO IO, Port A
J4
xpa[5]
D IO ST PD LSR
IO GPIO IO, Port A
C5
xpa[6]
D IO ST PD LSR
IO GPIO IO, Port A
F5
xpa[7]
D IO ST PD LSR
IO GPIO IO, Port A
Port B / DISPLAY / UART
xpb[0]
IO GPIO IO, Port B
mpmc_stcs1mw[0
]*
I
static memory chip memory width setting for boot loader
0: 8 bit data bus
1: 16 bit data bus
The value is latched at reset.
L10
dbop_c0
D IO ST PD LSR
O
DISPLAY control output
xpb[1]
IO GPIO IO, Port B
mpmc_stcs1pol*
I
static memory chip select polarity setting for boot loader
0: active LOW chip select
1: active high chip select
The value is latched at reset.
L11
dbop_c1
D IO ST PD LSR
O
DISPLAY control output
xpb[2]
IO GPIO IO, Port B
mpmc_stcs1pb*
I
static memory byte lane polarity setting for boot loader
0: HIGH for reads, LOW for writes, used for we_n access
1: LOW for reads, LOW for writes, used for upper and lower
byte access
The value is latched at reset.
K11
dbop_c2
D IO ST PD LSR
O
DISPLAY control output
xpb[3]
IO GPIO IO, Port B
mpmc_rel1config*
I
test mode configuration (for testing purpose only !!!)
The value is latched at reset.
K10
dbop_c3
D IO ST PD LSR
O
DISPLAY control output
xpb[4]
IO GPIO IO, Port B
K9
dbop_d[8]
D IO ST PD LSR
IO DISPLAY data input/output (high byte)
xpb[5]
IO GPIO IO, Port B
K12
dbop_d[9]
D IO ST PD LSR
IO DISPLAY data input/output (high byte)
xpb[6]
IO GPIO IO, Port B
uart_rxd
I
UART receive line
L12
dbop_d[10]
D IO ST PU LSR
IO DISPLAY data input/output (high byte)
xpb[7]
IO GPIO IO, Port B
uart_txd
O
UART transmit line
K13
dbop_d[11]
D IO ST PU LSR
IO DISPLAY data input/output (high byte)
Port C / DISPLAY / 2-WIRE SERIAL
xpc[0]
IO GPIO IO, Port C
IntBootSel*
I
BOOT LOADER source select input
1: internal ROM
0: external ROM/Flash
E5
dbop_d[0]
D IO ST PD LSR
IO DISPLAY data input/output (low byte)
C4
xpc[1]
D IO ST PD LSR
IO GPIO IO, Port C



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