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AS3525 Datasheet(PDF) 176 Page - ams AG |
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AS3525 Datasheet(HTML) 176 Page - ams AG |
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176 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 176 - 194 Ball Nr. BGA224 Ball Name PAD Type I/O Ball Description ssp_fssout O SSP master, frame or slave select C11 ssp_fssin D IO ST PU LSR I SSP slave, frame select ssp_clkout O SSP master, clock line H9 ssp_clkin D IO ST PU LSR I SSP slave, clock line D11 ssp_rxd D IO ST PU LSR I SSP receive data input J10 ssp_txd D IO ST PU LSR O SSP transmit data output NandFlash / IDE naf_d[0] IO NAND FLASH data line (low byte) C13 ide_hd[0] D IO ST PD LSR IO IDE data line (low byte) naf_d[1] IO NAND FLASH data line (low byte) A13 ide_hd[1] D IO ST PD LSR IO IDE data line (low byte) naf_d[2] IO NAND FLASH data line (low byte) B14 ide_hd[2] D IO ST PD LSR IO IDE data line (low byte) naf_d[3] IO NAND FLASH data line (low byte) D13 ide_hd[3] D IO ST PD LSR IO IDE data line (low byte) naf_d[4] IO NAND FLASH data line (low byte) B13 ide_hd[4] D IO ST PD LSR IO IDE data line (low byte) naf_d[5] IO NAND FLASH data line (low byte) C12 ide_hd[5] D IO ST PD LSR IO IDE data line (low byte) naf_d[6] IO NAND FLASH data line (low byte) G11 ide_hd[6] D IO ST PD LSR IO IDE data line (low byte) naf_d[7] IO NAND FLASH data line (low byte) B12 ide_hd[7] D IO ST PD LSR IO IDE data line (low byte) naf_d[8] IO NAND FLASH data line (high byte) C14 ide_hd[8] D IO ST PD LSR IO IDE data line (high byte) naf_d[9] IO NAND FLASH data line (high byte) E12 ide_hd[9] D IO ST PD LSR IO IDE data line (high byte) naf_d[10] IO NAND FLASH data line (high byte) F11 ide_hd[10] D IO ST PD LSR IO IDE data line (high byte) naf_d[11] IO NAND FLASH data line (high byte) D15 ide_hd[11] D IO ST PD LSR IO IDE data line (high byte) naf_d[12] IO NAND FLASH data line (high byte) F12 ide_hd[12] D IO ST PD LSR IO IDE data line (high byte) naf_d[13] IO NAND FLASH data line (high byte) E13 ide_hd[13] D IO ST PD LSR IO IDE data line (high byte) naf_d[14] IO NAND FLASH data line (high byte) D14 ide_hd[14] D IO ST PD LSR IO IDE data line (high byte) naf_d[15] IO NAND FLASH data line (high byte) E14 ide_hd[15] D IO ST PD LSR IO IDE data line (high byte) naf_cle O NAND FLASH command latch enable F14 ide_dmarq D IO ST LSR I IDE DMA request used for DMA data transfers between host and device naf_ale O NAND FLASH address latch enable F13 ide_iordy D IO ST LSR I IDE IO ready signal used by device to extend host data transfer cycles naf_wp_n O NAND FLASH write protect not G12 ide_intrq D IO ST PD LSR I IDE interrupt request used by device to interrupt the host controller |
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