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AS3525 Datasheet(PDF) 173 Page - ams AG |
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AS3525 Datasheet(HTML) 173 Page - ams AG |
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173 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 173 - 194 8.2.2 CTBGA224 Package Ball-out Figure 62 AS3525A Package Ball--out 1 23456 789 10 11 12 13 14 15 A jtag_tms xpc_7 xpc_3 xpa_2 mpmc_addr_3 mpmc_addr_9 mpmc_addr_17 mpmc_cas_n mpmc_bls_n_0 mpmc_data_5 mpmc_data_13 ide_ha_0 naf_d_1 dbop_d14 vdd_peri B jtag_tdi jtag_tck xpc_5 xpa_0 mpmc_addr_1 mpmc_addr_11 mpmc_addr_19 vss_mem vdd_mem mpmc_data_7 mpmc_data_15 naf_d_7 naf_d_4 naf_d_2 vss_peri C i2si_sdata_in jtag_trst_n xpc_6 xpc_1 xpa_6 mpmc_addr_7 mpmc_addr_15 vss_mem vdd_mem mpmc_data_9 ssp_fssout naf_d_5 naf_d_0 naf_d_8 dbop_d15 D i2si_lrck_out tmsel jtag_tdo xpc_4 xpa_4 mpmc_addr_5 mpmc_addr_13 mpmc_dqm_0 mpmc_stcs_n_0 mpmc_oe_n ssp_rxd ide_ha_2 naf_d_3 naf_d_14 naf_d_11 E clk_ext clk_sel i2si_sclk_out i2si_mclk xpc_0 mpmc_addr_8 mpmc_addr_14 mpmc_clk_0 mpmc_dycs_n_1 mpmc_data_1 mpmc_data_11 naf_d_9 naf_d_13 naf_d_15 naf_ce0_n F id_dig usb_vdda33t VBUS xpc_2 xpa_7 mpmc_addr_6 mpmc_addr_16 mpmc_cke_0 mpmc_we_n mpmc_data_3 naf_d_10 naf_d_12 naf_ale naf_cle naf_bsy_n G usb_dp usb_vssa33t dbop_d12 xpa_1 mpmc_addr_0 mpmc_addr_18 mpmc_clk_1 mpmc_data_10 mpmc_data_12 ide_reset_n naf_d_6 naf_wp_n naf_ce3_n naf_we_n xpd_3 H usb_dm usb_vssa33t dbop_d13 xpa_3 mpmc_addr_10 mpmc_addr_20 mpmc_data_8 ssp_clkout ide_ha_1 naf_ce1_n naf_re_n xpd_0 xpd_4 xpd_7 J usb_vssa33c usb_rkelvin_rext usb_vdda33c xpa_5 mpmc_addr_12 mpmc_cke_1 mpmc_ras_n mpmc_data_6 mpmc_data_14 ssp_txd naf_ce2_n xpd_1 xpd_2 xpd_5 xpd_6 K vdd_core nc DVDD nc mpmc_addr_4 mpmc_dycs_n_0 mpmc_bls_n_1 mpmc_data_4 xpb_4 xpb_3 xpb_2 xpb_5 xpb_7 SW_15V SW_3V L vss_core nc PwrUP mpmc_addr_2 mpmc_fbclkin mpmc_dqm_1 mpmc_stcs_n_1 mpmc_data_0 mpmc_data_2 xpb_0 xpb_1 xpb_6 CN_5V CP_5V VSS_3V M CLK_OUT XRES CSDA CSCL MCLK SDI SDO VREF HPCM BATTEMP ISINK VSS_15V VBAT_1V QLDO2 VSS_1V N INTRQ P_PVDD MSUP2 LOUTR LRCK SCLK LOUTL AVDD HPGND HPR BGND BVSS2 HPL CHG_IN CN_1V P DVSS LIN2R LIN1R MIC2_N MIC1_N MSUP1 BVSS AGND BVDD BVDD BVDD IOVDD RVDD CHG_OUT CP_1V R XIN_24M XOUT_24M LIN2L LIN1L MIC2_P MIC1_P AVSS BVSS LSPR LSPL UVDD PVDD XIN_32k XOUT_32k CVDD Note: PINs K2, L2 and K4 are reserved for production test purposes and must be left not connected for normal operation mode. 8.2.3 CTBGA224 Ball List Table 161 CTBGA224 Ball List Ball Nr. BGA224 Ball Name PAD Type I/O Ball Description M2 XRES resetext_n DO D IN ST O I XRES is generated by the PMU subsystem and connected to reset input (active low) on the BGA M1 CLK_OUT clk_int DO D IN ST O I CLK_OUT is output of 20-24MHz crystal oscillator clock and connected to clk_int on the BGA E1 clk_ext D IN ST PD I external clock input (10-26MHz) E2 clk_sel D IN ST PD I clock select 0 (low): clock from internal oscillator is used 1 (high): clock from pad clk_ext is used D2 tmsel D IN ST PD I test mode select For testing purpose only, has to be set to “0”. F1 id_dig D IN ST (PU) I USB mini receptacle identifier Has to be connected to USB jack ID pin. |
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