WM8143-10

Production Data

Wolfson Microelectronics

PD Rev 3f June 98

6

Pin Description

PIN

NAME

TYPE

DESCRIPTION

1

OP[0]

Digital OP

Tri-state digital 10-bit bi-directional bus. There are four modes:

2

OP1]

Digital OP

Tri-state:

when OEB = 1

3

OP[2]

Digital IO

4

OP[3]

Digital IO

5

OP[4]

Digital IO

6

OP[5]

Digital IO

7

OP[6]

Digital IO

8

OP[7]

Digital IO

9

OP[8]

Digital IO

10

OP[9]

Digital IO

Output ten-bit:

ten bit data is output from bus

Output 8-bit multiplexed:

data output on OP[9:2] at 2 * ADC

conversion rate

Input 8-bit:

control data is input on bits OP[9:2] in

parallel mode when SCK/RNW = 0.

MSB of the output word is OP[9], LSB is OP[0]

11

NRESET

Digital IP

Reset input, active low. This signal forces a reset of all internal registers and

selects whether serial control bus or parallel control bus is used ( see

SEN/STB)

12

AVDD

Analogue supply

Positive analogue supply (5V)

13

AGND

Analogue supply

Analogue ground (0V)

14

VRU

Analogue IP

15

VRB

Analogue OP

16

VRT

Analogue OP

voltages from an external 5V reference

17

VMID

Analogue OP

Buffered mid-point of ADC reference string.

18

VRLC

Analogue OP

Selectable analogue output voltage for RLC

19

BINP

Analogue IP

Blue channel input video

20

GINP

Analogue IP

Green channel input video

21

RINP

Analogue IP

Red channel input video

22

OEB

Digital IP

Output tri-state control:

all outputs enabled when OEB=0

23

SEN/STB

Digital IP

Serial interface:

enable, active high

Parallel interface:

strobe, active low

Latched on NRESET rising edge: If low then device control is by serial

interface, if high then device control is by parallel interface

24

SDI/DNA

Digital IP

Serial interface:

serial interface input data signal

Parallel interface:

high = data, low = address

25

SCK/RNW

Digital IP

Serial interface:

serial interface clock signal

Parallel interface:

high = OP[9:2] is output bus

low = OP[9:2] is input bus

26

RLC

Digital IP

Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is

required on each pixel then this pin can be tied high

27

VSMP

Digital IP

Video sample synchronisation pulse. This signal is applied synchronously with

MLCK to specify the point in time that the input is sampled. The timing of

internal multiplexing between the R, G and B channels is derived from this

signal

28

MCLK

Digital IP

Master clock. This clock is applied at eight, six, three or two times the input pixel

rate depending on the operational mode. MCLK is divided internally to define the

ADC sample rate and to provide the clock source for digital logic