WM8143-10CFTSLASHV datasheet(11/24 Pages) WOLFSON

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WM8143-10

Wolfson Microelectronics

PD.Rev 3f June 98

MCLK

Input video

VSMP

RLC

r,g,b

RLC on this pixel

No RLC on this pixel

r,g,b

Figure 7 RLC Timing

Video Sampling Options

The WM8143-10 can interface to CCD sensors using

six basic modes of operation (summarised in Table 3).

Mode configurations are controlled by a combination of

control bits and timing applied to MCLK and VMSP

pins. The default operational mode is mode 1: colour

with CDS enabled.

Colour Mode Definitions (Mode 1)

Figure 9 summarises the timing relationships. MCLK is

applied at twice the required ADC conversion rate.

Synchronisation of sampling and channel multiplexing

to the incoming video signal is performed by the VSMP

pulse (active high). The three input channels (R,G,B)

are sampled in parallel on the rising edge of MCLK

following

VSMP

pulse.

The

sampled

data

multiplexed into a single data stream at three times the

VSMP rate, passes through the internal pipeline and

emerges on the OP[9:0] bus. Both Correlated Double

Sampling (CDS) and Single Ended Sampling modes of

operation are available.

Monochrome Mode Definitions

One input channel is continuously sampled on the

rising edge of MCLK following a VSMP pulse. The user

can specify which input channel (R,G,B) is to be

sampled by writing to the WM8143-10 internal control

registers. There are four separate monochrome modes

with

different

maximum

sample

rates

and

CDS

availability.

Monochrome Mode (Mode 2)

Figure 10 summarises the timing relationships. The

timing in this mode is identical to mode 1 except that

one input channel is sampled three times (due to the

multiplexer being held in one position) and passes

through the device as three separate samples. The last

two samples can be ignored at the output OP[9:0].

Fast Monochrome Mode (Mode 3)

Figure 11 summarises the timing relationships. This

mode allows the maximum sample rate to be increased

MSPS.

This

achieved

altering

the

MCLK:VSMP ratio to 3:1. In this mode, the timing of

RS and CL must be fixed (refer to Table 3). The

sampled video data will pass through the internal

pipeline and emerge on the OP[9:0] bus.

Max. Speed Monochrome Mode (Mode 4)

Figure 12 summarises the timing relationships. This

mode allows the maximum sample rate to be increased

MSPS.

This

achieved

altering

the

MCLK:VSMP ratio to 2:1.

The latency through the

device is identical to modes 1 and 2. CDS is not

available in this mode.

Slow Colour Mode (Mode 5)

Figure 13 summarises the timing relationships. This

mode is identical to Mode 1 except that the MCLK to

VSMP ratio is 8 : 1 and the maximum sample rate is

1.5 MSPS. To obtain a ratio of 4:4 between the video

sample position and the reset sample position, Setup

to 10. The first three of the four output words are valid.

Slow Monochrome Mode (Mode 6)

Figure 14 summarises the timing relationships. This

mode is identical to mode 2 except that the MCLK to

VSMP ratio is 8 : 1 and the maximum sample rate is

1.5 MSPS. To obtain a ratio of 4:4 between the video

sample position and the reset sample position, Setup

set to 10. The first of the four output words is the only

valid output.

Input Impedance

The input impedance of the WM8143-10 is dependent

upon the sampling frequency of the input signal and the

gain that the PGA is set to. This is due to the effective

capacitance of the ‘sample and hold’ circuits (Figure 8).

RINP/VMID

PGA

VS/RS

VMID

S/H

Figure 8 Input Impedance S/H Circuit

When the VS/RS control is activated the switch closes

and the effective impedance of the input is 1/CF where

the value of C changes from 0.3pF for minimum gain to

WM8143-10CFT/V Datasheet(PDF) 11 Page - Wolfson Microelectronics plc

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