PCA9540BDP datasheet(5/22 Pages) NXP

5 / 22 page

PCA9540B_4

Product data sheet

Rev. 04 — 3 September 2009

5 of 22

NXP Semiconductors

PCA9540B

2-channel I2C-bus multiplexer

6.3 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9540B in

a reset condition until VDD has reached VPOR. At this point, the reset condition is released

and the PCA9540B registers and I2C-bus state machine are initialized to their default

states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be

lowered below 0.2 V to reset the device.

6.4 Voltage translation

The pass gate transistors of the PCA9540B are constructed such that the VDD voltage can

be used to limit the maximum voltage that will be passed from one I2C-bus to another.

Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph

was generated using the data speciﬁed in Section 10 “Static characteristics” of this

data sheet). In order for the PCA9540B to act as a voltage translator, the Vo(sw) voltage

should be equal to, or lower than the lowest bus voltage. For example, if the main bus was

running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be

equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at

Table 3.

Control register: Write—channel selection; Read—channel status

Command

XXXXX0

XXno channel selected

XXXXX

channel 0 enabled

XXXXX

channel 1 enabled

XXXXX1

no channel selected

00000000no channel selected;

power-up default state

(1) maximum

(2) typical

(3) minimum

Fig 7.

Pass gate voltage versus supply voltage

VDD (V)

2.0

5.5

4.5

3.0

4.0

002aaa964

3.0

2.0

4.0

5.0

Vo(sw)

(V)

1.0

3.5

5.0

2.5

(1)

(2)

(3)

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