PCA9541A_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 16 July 2009

23 of 41

NXP Semiconductors

PCA9541A

(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read

(MASTER 1 controlling the bus).

Fig 16. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization not

requested)

002aab610

1

1

1 A3 A2 A1 A0 0

slave address

R/W

S

START condition

A

acknowledge

from slave

000 AI 0001

command code register

auto

increment

A

acknowledge

from slave

P

STOP

condition

A

data Control register

0

0

0

0

0

1

0

0

After the STOP condition MASTER 1

is disconnected from the downstream

channel, and MASTER 0 is connected to

the downstream channel.

SCL_MST0

if the interrupt is not masked

(BUSLOSTMSK = 0)

INT1

INT0

if MASTER 1 was not idle at the switching moment

and the interrupt is not masked (BUSINITMSK = 0)

MASTER 0 has control of the bus

MASTER 1 has control of the bus

MASTER 0 must wait for the 'bus free time' value

before sending commands to the downstream devices.

acknowledge

from slave

BUSINIT

BUSON

MYBUS