PCF2123TS datasheet(22/55 Pages) NXP

22 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

22 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

If a new value of n is written before the end of the current timer period, then this value will

take immediate effect. NXP does not recommend changing n without ﬁrst disabling the

counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock,

therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into

the countdown counter which results in an undetermined countdown period for the ﬁrst

period. The countdown value n will, however, be correctly stored and correctly loaded on

subsequent timer periods.

When the countdown timer ﬂag is set, an interrupt signal on INT will be generated

provided that this mode is enabled. See Section 9.9.2 for details on how the interrupt can

be controlled.

When starting the timer for the ﬁrst time, the ﬁrst period will have an uncertainty which is a

result of the enable instruction being generated from the interface clock which is

asynchronous from the timer source clock. Subsequent timer periods will have no such

delay. The amount of delay for the ﬁrst timer period will depend on the chosen source

clock, see Table 29.

At the end of every countdown, the timer sets the countdown timer ﬂag (bit TF). Bit TF

may only be cleared by software. The asserted bit TF can be used to generate an

interrupt (INT). The interrupt may be generated as a pulsed signal every countdown

period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is

used to control this mode selection and the interrupt output may be disabled with bit TIE,

see Table 6.

In this example it is assumed that the timer ﬂag is cleared before the next countdown period

expires and that the pin INT is set to pulsed mode.

Fig 16. General countdown timer behavior

Table 29.

First period delay for timer counter value n

Timer source clock

Minimum timer period

Maximum timer period

4.096 kHz

n + 1

64 Hz

n + 1

1 Hz

− 1) + 1⁄64 Hz

n + 1

⁄

64 Hz

⁄

60 Hz

− 1) + 1⁄

64 Hz

n + 1

⁄

64 Hz

001aaf906

duration of first timer period after

enable may range from n

− 1 to n + 1

countdown value, n

timer source clock

countdown counter

INT

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