PCF2123TS datasheet(30/55 Pages) NXP

30 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

30 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

9.12 External clock test mode

A test mode is available which allows for on-board testing. In this mode it is possible to set

up test conditions and control the operation of the RTC.

The test mode is entered by setting bit EXT_TEST in register Control_1. Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the

signal applied to pin CLKOUT.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into a

known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP

must be cleared before the prescaler can operate again.)

From a stop condition, the ﬁrst 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operation example:

1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).

2. Set STOP (Control_1, bit STOP = 1).

3. Clear STOP (Control_1, bit STOP = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to pin CLKOUT.

6. Read time registers to see the ﬁrst change.

Table 39.

Effect of correction pulses

Frequency (Hz)

Effect of correction

CLKOUT

32768

no effect

16384

no effect

8192

no effect

4096

no effect

2048

no effect

1024

no effect

effected

Time source clock

4096

no effect

effected

⁄60

effected

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