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SC68C752B Datasheet(PDF) 39 Page - NXP Semiconductors |
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SC68C752B Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 48 page ![]() SC68C752B_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 20 January 2010 39 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Fig 20. Receive ready timing in FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 002aab092 first byte that reaches the trigger level Stop bit parity bit td15 RXA, RXB RXRDYA, RXRDYB CS (read) active data ready Start bit data bits (0 to 7) active td16 Fig 21. Transmit timing D0 D1 D2 D3 D4 D5 D6 D7 active transmitter ready active 16 baud rate clock 002aab093 td14 Start bit td12 TXA, TXB IRQ CS (write) data bits (0 to 7) active td13 5 data bits 6 data bits 7 data bits parity bit Stop bit next data Start bit |
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