M68HC05 datasheet(74/128 Pages) FREESCALE

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Technical Data

MC68HC05J1A — Rev. 3.0

Multifunction Timer

RTIE — Real-Time Interrupt Enable Bit

This read/write bit enables real-time interrupts.

1 = Real-time interrupts enabled

0 = Real-time interrupts disabled

TOFR — Timer Overflow Flag Reset Bit

Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always

reads as logic 0. Reset clears TOFR.

RTIFR — Real-Time Interrupt Flag Reset Bit

Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR

always reads as logic 0. Reset clears RTIFR.

RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0

These read/write bits select one of four RTI rates, as shown in

Table 8-1. Because the selected RTI output drives the COP

watchdog, changing the real-time interrupt rate also changes the

counting rate of the COP watchdog. Reset sets RT1 and RT0.

NOTE:

Changing RT1 and RT0 when a COP timeout is imminent or uncertain

may cause a real-time interrupt request to be missed or an additional

real-time interrupt request to be generated. Clear the COP timer just

before changing RT1 and RT0.

Table 8-1. Real-Time Interrupt Rate Selection

RT1:RT0

Number

of Cycles

to RTI

RTI

Period(1)

1. At 2-MHz bus, 4-MHz XTAL, 0.5

µs per cycle

Number

of Cycles

to COP Reset

COP Timeout

Period(1)

0 0

214 = 16,384

8.2 ms

217 = 131,072

65.5 ms

0 1

215 = 32,768

16.4 ms

218 = 262,144

131.1 ms

1 0

216 = 65,536

32.8 ms

219 = 524,288

262.1 ms

1 1

217 = 131,072

65.5 ms

220 = 1,048,576

524.3 ms

Freescale Semiconductor, Inc.

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