M68HC05 datasheet(79/128 Pages) FREESCALE

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Instruction Set

Addressing Modes

MC68HC05J1A — Rev. 3.0

Technical Data

Instruction Set

9.3.1 Inherent

Inherent instructions are those that have no operand, such as return

from interrupt (RTI) and stop (STOP). Some of the inherent instructions

act on data in the CPU registers, such as set carry flag (SEC) and

increment accumulator (INCA). Inherent instructions require no operand

address and are one byte long.

9.3.2 Immediate

Immediate instructions are those that contain a value to be used in an

operation with the value in the accumulator or index register. Immediate

instructions require no operand address and are two bytes long. The

opcode is the first byte, and the immediate data value is the second byte.

9.3.3 Direct

Direct instructions can access any of the first 256 memory locations with

two bytes. The first byte is the opcode, and the second is the low byte of

the operand address. In direct addressing, the CPU automatically uses

$00 as the high byte of the operand address.

9.3.4 Extended

Extended instructions use three bytes and can access any address in

memory. The first byte is the opcode; the second and third bytes are the

high and low bytes of the operand address.

When using the Motorola assembler, the programmer does not need to

specify whether an instruction is direct or extended. The assembler

automatically selects the shortest form of the instruction.

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M68HC05 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc