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PIC24F04KA201 Datasheet(PDF) 124 Page - Microchip Technology

Part # PIC24F04KA201
Description  14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP??Technology
PDF  224 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC24F04KA201 Datasheet(HTML) 124 Page - Microchip Technology

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PIC24F04KA201 FAMILY
DS39937B-page 122
Preliminary
© 2009 Microchip Technology Inc.
REGISTER 15-2:
SPI1CON1: SPI1 CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented:
Read as ‘0’
bit 12
DISSCK:
Disable SCK1 pin bit (SPI Master modes only)
1
= Internal SPI clock is disabled, pin functions as I/O
0
= Internal SPI clock is enabled
bit 11
DISSDO:
Disables SDO1 pin bit
1
= SDO1 pin is not used by module; pin functions as I/O
0
= SDO1 pin is controlled by the module
bit 10
MODE16:
Word/Byte Communication Select bit
1
= Communication is word-wide (16 bits)
0
= Communication is byte-wide (8 bits)
bit 9
SMP:
SPI1 Data Input Sample Phase bit
Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPI1 is used in Slave mode.
bit 8
CKE:
SPI1 Clock Edge Select bit(1)
1
= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0
= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7
SSEN:
Slave Select Enable bit (Slave mode)
1
=SS1 pin used for Slave mode
0
=SS1 pin not used by module; pin controlled by port function
bit 6
CKP:
Clock Polarity Select bit
1
= Idle state for clock is a high level; active state is a low level
0
= Idle state for clock is a low level; active state is a high level
bit 5
MSTEN:
Master Mode Enable bit
1
= Master mode
0
=Slave mode
bit 4-2
SPRE<2:0>:
Secondary Prescale bits (Master mode)
111
= Secondary prescale 1:1
110
= Secondary prescale 2:1
.
.
.
000
= Secondary prescale 8:1
Note 1:
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).



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