PIC24F04KA201 datasheet(127/224 Pages) MICROCHIP

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Preliminary

DS39937B-page 125

PIC24F04KA201 FAMILY

16.0

INTER-INTEGRATED CIRCUIT

(I2C™)

The Inter-Integrated Circuit (I2C™) module is a serial

interface

useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial data EEPROMs, display drivers,

A/D Converters, etc.

The I2C module supports these features:

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address, as defined in the I2C protocol

• Clock stretching to provide delays for the

processor to respond to a slave data request

• Both 100 kHz and 400 kHz bus specifications

• Configurable address masking

• Multi-Master modes to prevent loss of messages

in arbitration

• Bus Repeater mode, allowing the acceptance of

all messages as a slave regardless of the address

• Automatic SCL

Figure 16-1 illustrates a block diagram of the module.

16.1

Pin Remapping Options

The I2C module is tied to a fixed pin. To allow flexibility

with peripheral multiplexing, the I2C1 module in 20-pin

devices can be reassigned to the alternate pins,

designated as SCL1 and SDA1 during device

configuration.

Pin assignment is controlled by the I2C1SEL

Configuration bit. Programming this bit (= 0) multiplexes

the module to the SCL1 and SDA1 pins.

16.2

Communicating as a Master in a

Single Master Environment

The details of sending a message in Master mode

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

Assert a Start condition on SDA1 and SCL1.

Send the I2C device address byte to the slave

with a write indication.

Wait for and verify an Acknowledge from the

slave.

Send the first data byte (sometimes known as

the command) to the slave.

Wait for and verify an Acknowledge from the

slave.

Send the serial memory address low byte to the

slave.

Repeat steps 4 and 5 until all data bytes are

sent.

Assert a Repeated Start condition on SDA1 and

SCL1.

Send the device address byte to the slave with

a read indication.

10. Wait for and verify an Acknowledge from the

slave.

11. Enable master reception to receive serial

memory data.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

13. Generate a Stop condition on SDA1 and SCL1.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on the

Inter-Integrated Circuit, refer to the

“PIC24F

Family

Reference

Manual”

Section 24. “Inter-Integrated Circuit

(I2C™)”

(DS39702).

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