IR3870MBF datasheet(16/20 Pages) IRF

16 / 20 page

IR3870MBF

This capacitor has 9mΩ ESR which leaves

margin for the voltage drop of the ESL during

load step up. The typical ESL for this capacitor is

around 2nH. Refer to Output Capacitor Selection

section for all ceramic capacitor solution.

LAYOUT RECOMMENDATION

Bypass Capacitor:

One 1uF high quality ceramic capacitor should

be placed as near VCC pin as possible. The

other end of capacitor can be connected to a

via or connected directly to GND plane. Use a

GND plane instead of thin trace to the GND pin

because this thin traces have too much higher

impedance. A 1uF is recommended for both

V5 and PVCC and repeat the layout procedure

above for those signals.

Charge Pump:

We recommend that D1, D2 and CCPO be

placed as close to the CPO and PVCC pins as

possible. If those components can not be

placed on the same layer as IR3870, a

minimum of two vias are needed for the

connection of CCPO and CPO pin and the

connection of D2 and PVCC.

Boot Circuit:

CBOOT should be placed near the BOOT and

PHASE pins to reduce the impedance when the

upper MOSFET turns on. DBOOT does not need

to be close to CBOOT because the average

current to charge CBOOT is small during the on

time of lower MOSFET.

Power Stage:

Figure 19 shows the flowing current path for

the on and off periods. The on time path has

low average DC current with high AC current.

Therefore, it is recommended to place the input

ceramic capacitor, upper, and lower MOSFET

in a tight loop as shown in Figure 19.

The purpose of the tight loop from the input

ceramic capacitor is to suppress the high

frequency (10MHz range) switching noise and

reduce Electromagnetic Interference (EMI). If

this path has high inductance, the circuit will

cause voltage spikes and ringing, and increase

the switching loss. The off time path has low

AC and high average DC current. Therefore, it

should be laid out with a tight loop and wide

trace at both ends of the inductor. Lowering the

loop resistance reduces the power loss. The

typical resistance value of 1-ounce copper

thickness is 0.5mΩ per square inch.

Figure 19. Current Path of Power Stage

IR3870MBF Datasheet(PDF) 16 Page - International Rectifier

IR3870MBF Datasheet(HTML) 16 Page - International Rectifier

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL