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68HC05CL16 Datasheet(PDF) 109 Page - Motorola, Inc |
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68HC05CL16 Datasheet(HTML) 109 Page - Motorola, Inc |
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109 / 145 page  June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 PHASE-LOCKED LOOP MOTOROLA REV 2.0 13-3 Figure 13-1. Phase Lock Loop Block Diagram The phase comparator compares the rising edge of a 8kHz reference signal derived from the 32kHz crystal clock to the rising edge of the VCO clock after being divided by the divider. When there is a phase difference between the two signals, the phase comparator output will adjust the DC level input to the VCO to change the VCO frequency, see Figure 13-2. Figure 13-2. Typical Waveform for PLL 32 kHz VCO Phase Detector Divider Vss External Capacitor XFC 8 kHz PON PCLK FREQ1 FREQ0 PCSR Frequency Select System clock CLID clock (1.8MHz) 32kHz MUX R1 OSC DIVIDE BY 4 MUX PLLT PLLT_IN 32kHz PLL_CLK OSCILLATOR Reference Signal 8 kHz VCO out After divider Phase Output VCO in Detector |
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