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MAC7200 Datasheet(PDF) 264 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 264 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
186
Freescale Semiconductor
— Access Priority (PR)
→ 2'b00 (lowest priority)
— Read/Write (RW)
→ 1'b1 (write access)
— Word Size (SZ)
→ 3'b0xx (32-bit, 16-bit, 8-bit)
— Access Count (CNT)
→ 14'h0000 or 14'h0001(single access)
NOTE
Access Count (CNT) of 14'h0000 or 14'h0001 will perform a single access.
3. Initialize the Read/Write Access Data Register (RWD) through the JTAG access method outlined
in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the Nexus Register
Index of 0xA (see Table 11-21). Configure as follows:
—Write Data
→ 32'hxxxxxxxx (write data)
4. The Nexus block will then arbitrate for the AHB and transfer the data value from the RWD Register
to the memory mapped address in the Read/Write Access Address Register (RWA).
When the access has completed without error (ERR=1'b0), the Nexus block asserts the RDY pin
(see Table 11-13 for detail on RDY) and clears the DV bit in the RWCS Register. This indicates
that the device is ready for the next access.
NOTE
Only the RDY pin as well as the DV and ERR bits within the RWCS provide
Read/Write Access status to the external development tool. The
development tool needs to provide at least one clock after entering the
Run-Test-Idle state to ensure that the RDY pin is asserted.
11.11.5.3.2
Block Write Access
1. For a block write access, follow Steps 1, 2, and 3 outlined in Section 11.11.5.3.1, “Single Write
Access,” to initialize the registers, using a value greater than one (14'h0001) for the CNT field in
the RWCS Register.
2. The Nexus block will then arbitrate for the AHB and transfer the first data value from the RWD
Register to the memory mapped address in the Read/Write Access Address Register (RWA).
When the transfer has completed without error (ERR=1'b0), the address from the RWA Register is
incremented to the next word size (specified in the SZ field) and the number from the CNT field is
decremented. The Nexus block will then assert the RDY pin. This indicates that the device is ready
for the next access.
NOTE
The actual RWA value as well as the CNT field within the RWCS are not
changed when executing a block write access. The original values can be
read by the external development tool at any time.
3. Repeat Step 3 in Section 11.11.5.3.1, “Single Write Access,” until the internal CNT value is zero
(0). When this occurs, the DV bit within the RWCS will be cleared to indicate the end of the block
write access.



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