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MAC7200 Datasheet(PDF) 278 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 278 Page - Freescale Semiconductor, Inc

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The SPP DMA Controller Module (SPP_DMA2)
MAC7200 Microcontroller Family Reference Manual, Rev. 2
200
Freescale Semiconductor
7. TCD1b executes a scatter-gather operation, and reloads its TCD descriptor with TCD1a
8. TCD1a has the TCD.start bit cleared in the descriptor
Once the peripheral requests another transfer, the series of steps repeats.
Basically, the TCDs ping-pong between each other, with the throttling of block/frame transfers done by
the peripheral (hardware request) or by software (software request).
12.1.6.5
TCD Memory Initialization
As the TCD Memory does not have ECC, there is no requirement to initialize the memory in a specific
manner.
12.2
The SPP DMA Controller Module (SPP_DMA2)
This section provides a more detailed description of the generice SPP DMA Controller Module.
The DMA (Direct Memory Access) is a second-generation platform module capable of performing
complex data transfers with minimal intervention from a host processor via “n” programmable channels.
Intended for use as part of the Standard Product Platform (SPP), the hardware microarchitecture includes
a dma_engine which performs source and destination address calculations, and the actual data movement
operations, along with a local memory containing the transfer control descriptors (TCD) for the channels.
This SRAM-based implementation is utilized to minimize the overall module size.
Figure 12-1 is a block diagram of the DMA module.
Table 12-3. DMA Register Summary
DMA Register
Register “Mirrors”
Purpose
DMACR
--
DMA Control Register
DMAES
--
DMA Error Status
DMAERQH/L
DMASERQ
DMACERQ
DMA Enable Request
DMAEEIH/L
DMASEEI
DMACEEI
DMA Enable Error Interrupt
DMAINTH/L
DMACINT
DMA Interrupt Request
DMAERRH/L
DMACERR
DMA Error
DCHPRIn
--
DMA Channel n Priority
TCDnn
--
Transfer Control Descriptor nn



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