MAC7200 datasheet(274/976 Pages) FREESCALE

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Overview of the MAC7200 Implementation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

196

Freescale Semiconductor

12.1.6.2

General Operation of the DMA

1. The channel is initialized by software loading the transfer control descriptor into the DMA2’s

programming model, memory-mapped through the IPS space, and implemented as local memory.

2. The channel is activated, either explicitly by software, a peripheral request or a linkage from

another channel.

3. The contents of the transfer control descriptor for the activated channel is read from the local

memory and loaded into the dma2_engine’s registers.

4. The dma2_engine executes the data transfer defined by the inner minor loop, reading from the

source and writing to the destination.

5. At the conclusion of the minor loop’s execution, certain fields of the transfer control descriptor are

restored from the local memory.

The entire process (steps 1-5) is repeated until the outer major loop’s iteration count is exhausted. At that

time, additional processing steps are completed, e.g., the optional assertion of an interrupt request

signaling the transfer’s completion, final adjustments to the source and destination addresses, etc.

12.1.6.3

Configuring the DMA

Configuration of the DMA is divided into four areas:

— Configuring the arbitration and system loading

— Error signalling

— DEBUG mode behavior

— Transfer Control Descriptor (TCD)

— Channel completion

— Choosing a channel activation method for each channel

12.1.6.3.1

Arbitration and System Loading

There are four arbitration schemes available, all of which can be configured by using the DMACR register.

1. Choose a channel priority scheme that fits your application:

— Fixed-priority with Channel 0 preemption. To use this scheme, write EFPRI=1, ECH0P=1.

— Fixed-priority with high priority Channel 0. To use this scheme, write EFPRI=1, ECH0P=0.

— Round-robin with Channel 0 preemption. To use this scheme, write EFPRI=0, ECH0P=1.

— Round-robin with high priority Channel 0. To use this scheme, write EFPRI=0, ECH0P=0.

2. If a fixed-priority scheme is chosen, choose the priority for each channel by writing the DCHPRIn

registers.

3. For each channel, choose the relative priority of the DMA transfers over bus accesses from the

ARM7 core and/or debugger. Write the ‘bwc[1:0]’ field in Word 7 of the channel’s TCD (Transfer

Control Descriptor). This field controls how much bandwidth the DMA consumes for each access

in a minor loop. In this manner, it is possible to specify highest priority (bwc[1:0]=00) to lowest

priority (bwc[1:0]=11)

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