S3C70F2/C70F4/P70F4

ELECTRICAL DATA

14-7

Table 14-7. RAM Data Retention Supply Voltage in Stop Mode

(T

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply voltage

V

DDDR

–

1.8

–

5.5

V

Data retention supply current

I

DDDR

V

–

0.1

10

µA

Release signal set time

t

SREL

–

0

–

–

µs

Oscillator stabilization wait

t

WAIT

Released by

RESET

–

2

–

ms

Released by interrupt

–

(2)

–

ms

NOTES:

1.

During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-

up.

2.

Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

TIMING WAVEFORMS

RESET

EXECUTION OF

STOP INSTRUCTION

DATA RETENTION MODE

STOP MODE

INTERNAL RESET

OPERATION

IDLE MODE

OPERATING

MODE

Figure 14-2. Stop Mode Release Timing When Initiated by

RESET

RESET