S3P70F4 OTP

S3C70F2/C70F4/P70F4

16–10

Table 16-10. RAM Data Retention Supply Voltage in Stop Mode

(T

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply voltage

V

DDDR

–

2.0

–

5.5

V

Data retention supply current

I

DDDR

V

–

0.1

10

µA

Release signal set time

t

SREL

–

0

–

–

µs

Oscillator stabilization wait

t

WAIT

Released by

RESET

–

–

ms

Released by interrupt

–

(2)

–

ms

NOTES:

1.

During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.

2.

Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.