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VSC060

Data Sheet

Revision 4.1

January 2008

3.2

Control Register Definitions

The control register definitions provides a bit-level description of all register bits, including power on and

default values. The terms set and assert refer to bits that are programmed to a binary 1. The terms reset, de-

assert, and clear refer to bits that are programmed to a binary 0. Reserved bits are represented by RES and

always return an unknown value. These bits should be masked. Bits that are reserved should never be set to

a binary 1, because these bits may be defined in future versions of the device.

3.2.1

00h: General-Purpose I/O Port 0 Data (GPD0)

The following table shows the bit assignments for the General-Purpose I/O Port 0 Data register.

GPD0

Address:

00h

Reset Value:

XXXX_XXXXb

Bit

Bit Label

Access

Description

7:0

GPD0.7–0

R/W

General-Purpose Data

When the I/O pin is enabled as an output, writing these bits determines the data value

that will be present on the corresponding I/O pin.

If the I/O pin is enabled as an input, reading these register bits represent the current

voltage applied to the pin. At no time do the bits directly represent the value latched

into the data register.

If a pin is enabled as an input and there is no signal applied, weak internal pull-up

resistors hold the pin at a binary 1.

After a reset or power on, the register bits are set to a binary 1, however, the value

returned from a register read is the level applied to the pin since each pin is an input

by default.

Figure 3. I/O Port Block Diagram

Filter

GPD Read Data

GPD Write Data

DD Write Data

DD Read Data

I/O Port

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