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ST10F272Z2 Datasheet(PDF) 30 Page - STMicroelectronics |
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ST10F272Z2 Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 189 page  Internal Flash memory ST10F272Z2 30/189 5.4 Register description 5.4.1 Flash control register 0 low The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High (FCR0H) is used to enable and to monitor all the write operations on the IFLASH. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only. FCR0L (0x08 0000) FCR Reset Value: 0000h: 15 14 13 12 11 10 987 65432 10 reserved LOCK res. res. BSY0 res. RR Table 8. Flash control register 0 low Bit Function BSY0 Bank 0 Busy (IFLASH) This bit indicates that a write operation is running on Bank 0 (IFLASH). It is automatically set when bit WMS is set. Setting Protection operation sets bit BSY0 (since protection registers are in this Block). When this bit is set, every read access to Bank 0 will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend this bit is automatically reset and the Bank returns to read mode. After a Program or Erase Resume this bit is automatically set again. LOCK Flash Registers Access Locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY0 bit is reset. |
Similar Part No. - ST10F272Z2_08 |
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Similar Description - ST10F272Z2_08 |
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