R28 datasheet(76/473 Pages) RENESAS

76 / 473 page

R8C/28 Group, R8C/29 Group

7. Programmable I/O Ports

Rev.2.10

Sep 26, 2008

Page 57 of 441

REJ09B0279-0210

Figure 7.6

PDi (i = 1, 3, 4) Register

Figure 7.7

Pi (i = 1, 3, 4) Register

Port Pi Direction Register (i = 1, 3, 4)

(1, 2)

Symbol

Address

After Reset

PD1

00E3h

00h

PD3

00E7h

00h

PD4

00EAh

00h

Bit Symbol

Bit Name

Function

NOTES:

PDi_6

PDi_7

Port Pi_7 direction bit

PDi_5

Port Pi_5 direction bit

Port Pi_6 direction bit

b3 b2

PDi_2

b1 b0

PDi_1

PDi_0

b7 b6 b5 b4

0 : Input mode

(functions as an input port)

1 : Output mode

(functions as an output port)

Port Pi_0 direction bit

Port Pi_4 direction bit

Port Pi_2 direction bit

PDi_4

Bits PD4_0 to PD4_4, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.

If it is necessary to set bits PD4_0 to PD4_4, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0.

Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU.

If it is necessary to set bits PD3_0 to PD3_2 and PD3_6, set to 0 (input mode). When read, the content is 0.

PDi_3

Port Pi_3 direction bit

Port Pi_1 direction bit

Port Pi Register (i = 1, 3, 4)

(1, 2)

Symbol

Address

After Reset

00E1h

00h

00E5h

00h

00E8h

00h

Bit Symbol

Bit Name

Function

NOTES:

2. Bits P4_0, P4_1, P4_3, and P4_4, in the P4 register are unavailable on this MCU.

If it is necessary to set bits P4_0, P4_1, P4_3, and P4_4, set to 0 (“L” level). When read, the content is 0.

Pi_7

Pi_6

Bits P3_0 to P3_2 and P3_6 in the P3 register are unavailable on this MCU.

If it is necessary to set bits P3_0 to P3_2 and P3_6, set to 0 (“L” level). When read, the content is 0.

b3 b2 b1 b0

Pi_1

Pi_5

Pi_0

Pi_2

Pi_4

Pi_3

b7 b6 b5 b4

Port Pi_0 bit

Port Pi_1 bit

Port Pi_7 bit

Port Pi_5 bit

Port Pi_4 bit

Port Pi_3 bit

Port Pi_6 bit

Port Pi_2 bit

The pin level of any I/O port w hich is set

to input mode can be read by reading the

corresponding bit in this register. The pin

level of any I/O port w hich is set to output

mode can be controlled by w riting to the

corresponding bit in this register.

0 : “L” level

1 : “H” level

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