R28 datasheet(82/473 Pages) RENESAS

82 / 473 page

R8C/28 Group, R8C/29 Group

7. Programmable I/O Ports

Rev.2.10

Sep 26, 2008

Page 63 of 441

REJ09B0279-0210

X: 0 or 1

NOTES:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Set bit 0 (reserved bit) in the PMR register to 0.

3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.

X: 0 or 1

NOTES:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Set the SSISEL bit in the PMR register to 1 (P1_6).

3. When the SOOS bit is set to 1 (N-channel open drain output) and BIDE bit is set to 0 (standard mode) in the SSMR2 register,

this pin is set to N-channel open drain output.

X: 0 or 1

NOTES:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Set bit 0 (reserved bit) in the PMR register to 0.

3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.

Table 7.12

Port P1_5/RXD0/(TRAIO)/(INT1)

PD1

TRAIOC

TRAMR

INTEN

Function

Bit

PD1_5

TIOSEL

TOPCR(3)

TMOD2

TMOD1

TMOD0

INT1EN

Setting

Value

XXX

Input port(1)

10010

00000

XXX

Output port

0000

XXX

RXD0 input(1)

Other than 001b

Other than 000b, 001b

TRAIO input(1)

00001

INT1(2)

10011

Other than 000b, 001b

TRAIO input/INT1(1, 2)

0001

TRAIO pulse output

Table 7.13

Port P1_6/CLK0/(SSI)

PD1

U0MR

PMR

Clock Synchronous Serial I/O with Chip

Select (Refer to Table 16.4

Association between

Communication Modes and I/O Pins.)

Function(3)

Bit

PD1_6

CKDIR

SMD2

SMD1

SMD0

IICSEL

SSI output control

SSI input control

Setting

Value

Input port(1)

Other than 001b

Output port

CLK0 output

CLK0 input(1)

SSI output(2)

SSI input(1, 2)

Table 7.14

Port P1_7/TRAIO/INT1

PD1

TRAIOC

TRAMR

INTEN

Function

Bit

PD1_7

TIOSEL

TOPCR(3)

TMOD2

TMOD1

TMOD0

INT1EN

Setting

Value

Input port(1)

010

000

Output port

000

Other than 000b, 001b

TRAIO input(1)

000

INT1(2)

010

Other than 000b, 001b

TRAIO input/INT1(1, 2)

TRAIO pulse output

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