R28 datasheet(85/473 Pages) RENESAS

85 / 473 page

R8C/28 Group, R8C/29 Group

7. Programmable I/O Ports

Rev.2.10

Sep 26, 2008

Page 66 of 441

REJ09B0279-0210

X: 0 or 1

NOTES:

1. Pulled up by setting the PU07 bit in the PUR0 register to 1.

2. Set the SSISEL bit in the PMR register to 0 (P3_3).

3. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open drain output).

4. N-channel open drain output by setting the NCH bit in the U1C0 register to 1.

X: 0 or 1

NOTE:

1. Set the U1PINSEL bit in the PMR register to 1 (enabled).

Table 7.20

Port P3_7/TRAO/SSO/RXD1/(TXD1)

PD3

PMR

Clock Synchronous Serial I/O with Chip

Select (Refer to Table 16.4

Association between

Communication Modes and I/O Pins.)

TRAMR

UART1 setting

Function(3)

Bit

PD3_7

IICSEL

SSO output control

SSO input control

TOENA

−

Setting

Value

Other than TXD1, RXD1

usage conditions

Input port(1)

Other than TXD1, RXD1

usage conditions

Output port

Refer to Table 7.21Port

P3_7 UART1 Setting

Condition

TXD1 output(4)

Refer to Table 7.21Port

P3_7 UART1 Setting

Condition

RXD1 input(1)

Other than TXD1, RXD1

usage conditions

TRAO output

Other than TXD1, RXD1

usage conditions

SSO output(2)

Other than TXD1, RXD1

usage conditions

SSO input(2)

Table 7.21

Port P3_7 UART1 Setting Condition(1)

PINSR1

PMR

U1MR

Function

Bit

UART1SEL1

UART1SEL0

TXD1SEL

TXD1EN

SMD2

SMD1

SMD0

Setting

Value

001

TXD1 output

100

101

110

001

100

101

110

RXD1 input

Other than above

Other than TXD1, RXD1

usage conditions

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