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IP1206PBF Datasheet(PDF) 23 Page - International Rectifier

Part # IP1206PBF
Description  Synchronous Buck Multiphase Optimized LGA Power Block
PDF  30 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IP1206PBF Datasheet(HTML) 23 Page - International Rectifier

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2/26/2008
www.irf.com
23
iP1206PbF
Compensation
for
Current
Loop
(slave channel)
The
slave
error
amplifier
is
differential
transconductance
amplifier,
in
2-phase
configuration the main goal for the slave channel
feedback loop is to control the inductor current to
match the master channel inductor current as
well provides highest bandwidth and adequate
phase margin for overall stability. The following
analysis is valid for both using external current
sense resistors and using DCR of inductor.
The
transfer
function
of
power
stage
is
expressed by:
Where:
V
in=Input voltage
L
2=Output inductor
V
osc=Oscillator Peak Voltage
As shown the G(s) is a function of inductor
current. The transfer function for compensation
network is given by equation (21), when using a
series RC circuit as shown in Fig 23.
The loop gain function is:
)
(
V
sL
V
V
s
I
s
G
osc
in
e
L
20
*
)
(
)
(
2
2
-
-
-
-
=
=
L2
L1
C2
R2
RS2
RS1
Ve
IL2
IL1
Fb2
E/A2
Comp2
Vp2
)
(
sC
R
sC
R
R
g
R
s
V
s
D
s
s
m
s
e
21
1
*
*
)
(
)
(
2
2
2
2
1
2
-
-
-
-
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛ +
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
=
=
[
]
2
s
R
s
D
s
G
s
H
*
)
(
*
)
(
)
(
=
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛ +
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
=
osc
2
in
2
2
2
2
s
1
s
m
2
s
V
sL
V
sC
C
sR
1
R
R
g
R
s
H
*
*
*
*
*
)
(
Select a zero frequency for current loop (F
o2) 1.5
times larger than zero cross frequency for
voltage loop (F
o1).
From (22), R2 can be expressed as:
V
in=12V
V
osc=1.25V
g
m=2800umoh
L
2=1uH
R
s1=DCR=2.4mOhm
F
o2=60kHz
This results to : R
2=5.84K
The power stage of current loop has a dominant
pole (Fp) at frequency expressed by:
Where Rds(on1) is the on-resistance of control
FET, Rds(on2) is the on-resistance of
synchronous FET, RL is the DCR of output
inductance and D is the duty cycle
Req=9.48mOhm
Set the zero of compensator at 10 times the
dominant pole frequency FP, the compensator
capacitor, C2 can be expressed as:
C2=1nF
All designs should be tested for stability to verify
the calculated values.
1
O
2
O
F
5
1
F
*
%
.
≅
)
(
V
L
F
V
R
R
g
F
H
osc
O
in
s
m
O
22
1
*
*
*
2
*
*
*
)
(
2
2
2
1
2
-
-
-
-
=
=
π
)
(
V
V
L
F
R
g
R
in
osc
O
s
m
23
*
*
*
2
*
*
1
2
2
1
2
-
-
-
-
π
=
s
L
on
ds
eq
R
R
R
R
+
+
=
)
(
z
2
2
P
z
F
R
2
1
C
F
10
F
*
*
*
π
=
=
Fig. 23: The Compensation network for current loop
L
2
R
F
2
eq
P
*
π
=
L
2
on
ds
1
on
ds
eq
R
D
1
R
D
R
R
+
−
+
=
)
(
*
*
)
(
)
(



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