PPC8567CVTAUGGA datasheet(43/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet Interface and MII Management

Figure 22 shows the MII management AC timing diagram.

Figure 22. MII Management Interface Timing Diagram

MDC period

tMDC

400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO delay

tMDKHDX

(16*tplb_clk)-3

(16*tplb_clk)+3

3, 5

MDIO to MDC setup time

tMDDVKH

5—

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

—10

MDC fall time

tMDCF

—10

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data

outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect

to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high

(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F

(fall).

2. IEEE 802.3 standard specifies that the max MDC frequency to be 2.5MHz. The frequency is programmed through

MIIMCFG[MgmtClk].

3. This parameter is dependent on the platform clock speed. The delay is equal to 16 platform clock periods +/-3ns. With a

platform clock of 333MHz, the min/max delay is 48ns +/- 3ns.

4. Guaranteed by design

5. tplb_clk is the platform (CCB) clock period.

6. MDC to MDIO data valid tMDKHDV is a function of clock period and max delay time (tMDKHDX). (Min Setup time = Cycle

time – Max delay).

Table 38. MII management AC timing specifications (continued)

Parameters

Symbol

Min

Max

Unit

Notes

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