PPC8567CVTAUGGA datasheet(58/139 Pages) FREESCALE

58 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Figure 30 provides the AC test load for the I2C.

Figure 34. I2C AC Test Load

Figure 35 shows the AC timing diagram for the I2C bus.

Figure 35. I2C Bus AC Timing Diagram

Capacitive load for each bus line

—400

Note:

1.The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the START condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the tI2C

clock reference (K) going to the high (H) state or setup time.

2. As a transmitter, the MPC8568 provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP condition.

When the MPC8568 acts as the I2C bus master while transmitting, the MPC8568 drives both SCL and SDA. As long as the

load on SCL and SDA are balanced, the MPC8568 would not cause unintended generation of START or STOP condition.

Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay

time is required for the MPC8568 as transmitter, application note AN2919 referred to in note 4 below is recommended.

3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4.The requirements for I2C frequency calculation must be followed. Refer to Freescale application note AN2919, Determining

the I2C Frequency Divider Ratio for SCL

Table 47. I2C AC Electrical Specifications (continued)

At recommended operating conditions with OVDD of 3.3V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 46).

Parameter

Symbol 1

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SDA

SCL

tI2SXKL

tI2CL

tI2CH

tI2DXKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

PPC8567CVTAUGGA Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc

PPC8567CVTAUGGA Datasheet(HTML) 58 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL