PPC8567CVTAUGGA datasheet(131/139 Pages) FREESCALE

131 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

131

System Design Information

Each circuit should be placed as close as possible to the specific AVDD type pin being supplied to minimize

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD

type pin, which is on the periphery of 1023FC-PBGA the footprint, without the inductance of vias.

Figure 73 shows the PLL power supply filter circuits for all PLLs except SerDes PLL.

Figure 73. MPC8568E PLL Power Supply Filter Circuit

The AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of

the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the

AVDD_SRDS and AGND_SRDS ball to ensure it filters out as much noise as possible. The 0.003-µF

capacitor is closest to the ball, followed by the 2.2-µF capacitors, and finally the 1 ohm resistor to the board

supply plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces

should be kept short, wide and direct.

Figure 74. SerDes PLL Power Supply Filter

Note the following:

•AVDD_SRDS should be a filtered version of SCOREVDD.

•

The transmitter output signals on the SerDes interface are fed from the XVDD power plan.

•

Power: XVDD consumes less than 300mW. SCOREVDD + AVDD_SRDS consumes less than

750mW.

25.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

MPC8568E system, and the device itself requires a clean, tightly regulated source of power. Therefore, it

is recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD,

BVDD, OVDD, GVDD, and LVDD pin of the device. These decoupling capacitors should receive their

power from separate VDD,TVDD, BVDD, OVDD, GVDD, and LVDD and GND power planes in the PCB,

utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a

standard escape pattern. Others may surround the part.

VDD

AVDD

2.2

μF

2.2

μF

GND

Low ESL Surface Mount Capacitors

2.2

μF1 0.003 μF

AGND_SRDS

1.0

AVDD_SRDS

1. An 0805 sized capacitor is recommended for system initial bring-up.

SCOEVDD

2.2

μF1

PPC8567CVTAUGGA Datasheet(PDF) 131 Page - Freescale Semiconductor, Inc

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