PPC8567ECVTANJGA datasheet(26/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet Interface and MII Management

7.2

DUART AC Electrical Specifications

Table 22 provides the AC timing parameters for the DUART interface.

Ethernet Interface and MII Management

This section provides the AC and DC electrical characteristics for eTSEC, MII management and Ethernet

interface inside QUICC Engine. Note that eTSEC and QE Ethernet have the same DC/AC characteristics.

8.1

GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media

independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI

interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether

the GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compatible with the IEEE 802.3

standard. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface

(RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII

Input current

(VIN

1 = 0 V or V

IN = VDD)

IIN

—±10

μA

High-level output voltage

(OVDD = min, IOH = –100 μA)

VOH

OVDD – 0.2

—

Low-level output voltage

(OVDD = min, IOL = 100 μA)

VOL

—0.2

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3.

Table 22. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

CCB clock/1,048,576

baud

1,2

Maximum baud rate

CCB clock/16

baud

1,3

Oversample rate

—

1,4

Notes:

1. Guaranteed by design

2. CCB clock refers to the platform clock.

3. Actual attainable baud rate will be limited by the latency of interrupt processing.

4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16th sample.

Table 21. DUART DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

PPC8567ECVTANJGA Datasheet(PDF) 26 Page - Freescale Semiconductor, Inc

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