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PPC8567ECVTANJGA Datasheet(PDF) 31 Page - Freescale Semiconductor, Inc

Part # PPC8567ECVTANJGA
Description  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
PDF  139 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PPC8567ECVTANJGA Datasheet(HTML) 31 Page - Freescale Semiconductor, Inc

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
31
Ethernet Interface and MII Management
Figure 9 shows the GMII transmit AC timing diagram.
Figure 9. GMII Transmit AC Timing Diagram
8.2.2.2
GMII Receive AC Timing Specifications
Table 28 provides the GMII receive AC timing specifications.
EC_GTX_CLK125 duty cycle
tG125H/tG125
45
55
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input
signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect
to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design
Table 28. GMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period
tGRX
—8.0
—
ns
RX_CLK duty cycle
tGRXH/tGRX
40
—
60
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.5
—
—
ns
RX_CLK clock rise (20%-80%)
tGRXR
2
—1.0
2.0
ns
Table 27. GMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GTX_CLK
TXD[7:0]
tGTKHDX
tGTX
tGTXH
tGTXR
tGTXF
tGTKHDV
TX_EN
TX_ER



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