PPC8567ECVTANJGA datasheet(93/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

TDM/SI

19.2

TDM/SI AC Timing Specifications

Table 72 provides the TDM/SI input and output AC timing specifications.

Figure 60 provides the AC test load for the TDM/SI.

Figure 60. TDM/SI AC Test Load

Figure 61 represents the AC timing from Table 72. Note that although the specifications generally

reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the

active edge.

Input low voltage

VIL

—-0.3

0.8

Input current

IIN

0 V

≤ VIN ≤ OVDD

—

± 10

μA

Table 72. TDM/SI AC Timing Specifications 1

Characteristic

Symbol 2

Min

Max

Unit

TDM/SI outputs—External clock delay

tSEKHOV

211

TDM/SI outputs—External clock High Impedance

tSEKHOX

210

TDM/SI inputs—External clock input setup time

tSEIVKH

5—

TDM/SI inputs—External clock input hold time

tSEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes

from the high state (H) until outputs (O) are invalid (X).

Table 71. TDM/SI DC Electrical Characteristics (continued)

Characteristic

Symbol

Condition

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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