PPC8567ECVTANJGA datasheet(101/139 Pages) FREESCALE

101 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

101

Package and Pinout

Maximum solder ball diameter measured parallel to datum A.

Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

ParalleUsm measurement shall exclude any effect of mark on top surface of package

Capacitors may not be present on all devices.

Caution must be taken not to short capacitors or exposed metal capacitor pads on top of package.

22.3

Pinout Listings

Some of the non-QE signals are multiplexed with QE port pins, as follows:

PC[0]

UART_SOUT[1]

PC[1]

UART_RTS[1]

PC[2]

UART_CTS[1]

PC[3]

UART_SIN[1]

PC[11]

IRQ[8]

PC[12]

IRQ[9]/DMA_DREQ[3]

PC[13]

IRQ[10]/DMA_DACK[3]

PC[14]

IRQ[11]/DMA_DDONE[3]

PC[15]

DMA_DREQ[1]

PC[16]

DMA_DACK[1]

PC[17]

DMA_DDONE[1]

PC[18]

IIC2_SCL

PC[19]

IIC2_SDA

PD[28]

UART_SOUT[1]

PD[29]

UART_RTS[1]

PD[30]

UART_CTS[1]

PD[31]

UART_SIN[1]

This applies to both MPC8568E and MPC8568E. Note that for DUART1, there are two options. DUART0

is multiplexed with PCI Req/Grant pins.

PCI_REQ[3]

UART_CTS[0]

PCI_REQ[4]

UART_SIN[0]

PCI_GNT[3]

UART_RTS[0]

PCI_GNT[4]

UART_SOUT[0]

For MPC8568E, GPIO is multiplexed with the TSEC2 interface:

TSEC2_TXD[7:0]

GPOUT[0:7]

PPC8567ECVTANJGA Datasheet(PDF) 101 Page - Freescale Semiconductor, Inc

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