PPC8567ECVTANJGA datasheet(121/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

121

Clocking

23 Clocking

This section describes the PLL configuration of the MPC8568E. Note that the platform clock is identical

to the core complex bus (CCB) clock.

23.1

Clock Ranges

Table 80 provides the clocking specifications for the processor cores and Table 81 provides the clocking

specifications for the DDR/DDR2 memory bus. Table 82 provides the clocking specifications for the local

bus.

30. This pin requires an external 4.7-k

Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively

driven.

33. PF[21:22] are multiplexed as cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET

ASSERTION.

35. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down

to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as "No Connect"

or terminated through 2–10 K

Ω pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not connected to any

other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through POR config

pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI

device connected on the bus.

36.MDIC[0] is grounded through an 18.2-

Ω precision 1% resistor and MDIC[1] is connected to GVDD through an 18.2-Ω precision

1% resistor. These pins are used for automatic calibration of the DDR IOs.

39. If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI_CLK . Otherwise the processor

will not boot up.

41.These pins should be tied to SCOREGND through a 300 ohm resistor if the high speed interface is used.

43. It is highly recommended that unused SD_RX/SD_RX lanes should be powered down with lane_x_pd. Otherwise the receivers

will burn extra power and the internal circuitry may develop long term reliability problems.

44. See Section 25.9, “Guidelines for High-Speed Interface Termination.”

46. Must be high during HRESET. It is recommended to leave the pin open during HRESET since it has internal pullup resistor.

47. Must be pulled down with 4.7-k

Ω resistor.

48. This pin must be left no connect.

49. A pull-up on LGPL4 is required for systems that boot from local bus (GPCM)-controlled NOR Flash.

Table 80. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

800 MHz

1000 MHz

1333 MHz

Min

Max

Min

Max

Min

Max

e500 core processor frequency

533

800

533

1000

533

1333

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 23.2, “CCB/SYSCLK PLL Ratio,” and Section 23.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 79. MPC8567E Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

PPC8567ECVTANJGA Datasheet(PDF) 121 Page - Freescale Semiconductor, Inc

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