LPC1850 datasheet(39/84 Pages) NXP

39 / 84 page

LPC1850_30_20_10

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Objective data sheet

Rev. 1 — 3 January 2011

39 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.12.3.1

Features

• Interfaces to serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Data rates of up to 40 MB per second total.

• Supports DMA access.

7.12.4 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

• Secure Digital memory (SD version 3.0)

• Secure Digital I/O (SDIO version 2.0)

• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)

• Multimedia Cards (MMC version 4.4)

7.12.5 External Memory Controller (EMC)

The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for

asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it

can be used as an interface with off-chip memory-mapped devices and peripherals.

7.12.5.1

Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and NOR flash,

with or without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16/32 data and 24 address lines wide static memory support. On parts LPC1820/10

only 8/16 data lines are available.

• 16 bit and 32 bit wide chip select SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read

– Programmable Wait States

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

• Four chip selects for synchronous memory and four chip selects for static memory

devices.

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

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