LPC1850 datasheet(49/84 Pages) NXP

49 / 84 page

LPC1850_30_20_10

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Objective data sheet

Rev. 1 — 3 January 2011

49 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

In addition, the CREG block contains the part identification and part configuration

information.

7.17.2 System Control Unit (SCU)

The system control unit determines the function and electrical mode of the digital pins. By

default function 0 is selected for all pins with pull-up enabled.

Analog I/Os for the ADCs and the DAC as well as most USB pins are on separate pads

and are not controlled through the SCU.

7.17.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks may be

unrelated in frequency and phase and can have different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins.

Derived from each base clock may be multiple branch clocks. The branch clocks offer

very flexible control for power-management purposes. All branch clocks are outputs of

one of two Clock Control Units (CCUs) and can be controlled independently. Branch

clocks derived from the same base clock are synchronous in frequency and phase.

7.17.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1850/30/20/10 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.17.5 PLL0 (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.17.6 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop

to keep the CCO within its frequency range while the PLL is providing the desired output

frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output

clock. Since the minimum output divider value is 2, it is insured that the PLL output has a

50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be

enabled by software. The program must configure and activate the PLL, wait for the PLL

to lock, and then connect to the PLL as a clock source. The PLL settling time is 100

μs.

7.17.7 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals.

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