Analogue Control Interface

FX839

© 1997 Consumer Microcircuits Limited

7

D/839/4

1.5

General Description

The device comprises four groups of related functions: variable attenuators, digital to analogue converters, a

multiplexed analogue to digital converter with multiplexer, clock generator and four 8-bit magnitude

comparators with variable reference levels. These functions are all controlled by the 'C-BUS' serial interface

and are described below:

Variable Attenuators

The two variable attenuators have a range of 0 to -12dB and 0 to -6dB respectively and may be controlled

independently.

Digital to Analogue Converters

Three DACs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. In this

mode the 'C-BUS' data is transferred in a single byte. An option is provided to define any one or more of the

DAC resolutions to be 10 bits, then the DAC requires the transfer of two 'C-BUS' data bytes.

voltage is expressed as:

Where, n is the DAC resolution (8 or 10 bits) and DATA is the decimal value of the input code. For example: n

= 8 and binary code = 11111111 therefore DATA = 255

Any one of the three DAC input latches may be loaded by sending an address/command byte followed by one

or two data bytes to the 'C-BUS' interface. The data is then latched and the static voltage is updated at the

appropriate output.

When a DAC is disabled its output is defined as open-circuit.

Analogue to Digital Converter and ADC Clock Generator

A single successive approximation ADC is provided with four multiplexed inputs. In order to minimise the

sampling time of each input channel, a Sample and Hold circuit has not been included at the input of the ADC.

For the sampling to be accurate the input signal should not change significantly during the conversion time.

Since the typical application is for the monitoring of slowly changing control voltages this should not present

any problems. The maximum signal 'linear rate of change', 'S', can be quantified by the following expression

(for a maximum 1 bit error):

The programmable clock generator is intended to be flexible, making use of an external system clock signal or

has full control of the frequency scaling factor and this should be chosen such that the input clock frequency, at

the XTAL/CLOCK pin, divided by this factor is no more than 1MHz.