MPC8358E datasheet(75/95 Pages) FREESCALE

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MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3

Freescale Semiconductor

Clocking

Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock

divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock

divider ratio is controlled by LCRR[CLKDIV].

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped

frequency.

Table 67 provides the operating frequencies for the PBGA package under recommended operating

conditions (see Table 2). All frequency combinations shown in the table below may not be available.

Maximum operating frequencies depend on the part ordered, see Section 25.1, “Part Numbers Fully

Addressed by this Document,” for part ordering details and contact your Freescale sales representative or

authorized distributor for more information.

Table 66. Configurable Clock Units

Unit

Default

Frequency

Options

Security core

csb_clk/3

Off,

csb_clk1, csb_clk/2,

csb_clk/3

1 With limitation, only for slow csb_clk rates, up to 166 MHz.

PCI and DMA complex

csb_clk

Off,

csb_clk

Table 67. Operating Frequencies for the PBGA Package

Characteristic1

1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,

MCLK, LCLK[0:2], and

core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

400 MHz

Unit

e300 core frequency (

core_clk)

266–400

MHz

Coherent system bus frequency

(

csb_clk)

133–266

MHz

QUICC Engine frequency

(

ce_clk)

266–400

MHz

DDR and DDR2 memory bus frequency

(MCLK)2

2 The DDR data rate is 2x the DDR memory bus frequency.

100–133

MHz

Local bus frequency

(LCLK

n)3

3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1x or 2x

the

csb_clk frequency (depending on RCWL[LBCM]).

16.67–133

MHz

PCI input frequency (CLKIN or PCI_CLK)

25–66.67

MHz

Security core maximum internal operating frequency

133

MHz

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