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MPC8358E Datasheet(PDF) 83 Page - Freescale Semiconductor, Inc |
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MPC8358E Datasheet(HTML) 83 Page - Freescale Semiconductor, Inc |
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83 / 95 page  MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 83 Clocking The following steps describe how to use Table 74. See Example 1. 1. Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz. 2. Select a suitable CSB and core clock rates from Table 74. Copy the SPMF and CORE PLL configuration bits. 3. Select a suitable QUICC Engine block clock rate from Table 74. Copy the CEPMF and CEPDF configuration bits. 4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively. Example 1. Sample Table Use c5 æ æ 10000 0 33 — — 533 — ∞∞ c6 æ æ 10001 0 33 — — 566 — — ∞ 66 MHz CLKIN/PCI_SYNC_IN Options s1h 0011 0000110 æ æ 66 200 400 — ∞∞ ∞ s2h 0011 0000101 æ æ 66 200 500 — — ∞∞ s3h 0011 0000110 æ æ 66 200 600 — — — ∞ s4h 0100 0000011 æ æ 66 266 400 — ∞∞ ∞ s5h 0100 0000100 æ æ 66 266 533 — — ∞∞ s6h 0100 0000101 æ æ 66 266 667 — — — ∞ s7h 0101 0000010 æ æ 66 333 333 — ∞∞ ∞ s8h 0101 0000011 æ æ 66 333 500 — — ∞∞ s9h 0101 0000100 æ æ 66 333 667 — — — ∞ c1h æ æ 00101 0 66 — — 333 ∞∞ ∞ c2h æ æ 00110 0 66 — — 400 ∞∞ ∞ c3h æ æ 00111 0 66 — — 466 — ∞∞ c4h æ æ 01000 0 66 — — 533 — ∞∞ c5h æ æ 01001 0 66 — — 600 — — ∞ 1 The Conf No. consist of prefix, an index and a postfix. The prefix “s” and “c” stands for “syset” and “ce” respectively. The postfix “h” stands for “high input clock.’”The index is a serial number. SPMF CORE PLL CEPMF CEPDF Input Clock (MHz) CSB Freq (MHz) Core Freq (MHz) QUICC Engine Freq (MHz) 400 (MHz) 1000 0000011 01001 0 33 266 400 300 ∞ Table 74. Suggested PLL Configurations (continued) Conf No.1 SPMF CORE PLL CEPMF CEPDF Input Clock Freq (MHz) CSB Freq (MHz) Core Freq (MHz) QUICC Engine Freq (MHz) 400 (MHz) 533 (MHz) 667 (MHz) |
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