HT83F02 datasheet(26/64 Pages) HOLTEK

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HT83F02

Rev. 1.20

November 19, 2010

Master/Salve

(SIMEN=0)

Master (SIMEN=1)

Slave (SIMEN=1)

CSEN=1

CSEN=0

SCS line=0

(CSEN=1)

SCS line=1

(CSEN=1)

SCS

I, Z

SDO

OOOO

SDI

I, Z

SCK

L(CPOL=1)

H(CPOL=0)

L(CPOL=1)

H(CPOL=0)

I, Z

²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high)

SPI Interface Pin Status

· SPI Registers

The SIMDR A/B register is used to store the data be-

ing transmitted and received. There are two control

registers associated with the SPI interface, SIMC0

A/B and SIMC2 A/B and one data register known as

SIMDRA/B. The SIMC1 A/B register is not used by the

SPI function. Register SIMC0 A/B is used to control

the enable/disable function, the power down control

and to set the data transmission clock frequency. Reg-

ister SIMC2 A/B is used for other control functions

such as LSB/MSB selection, write collision flag etc.

The following gives further explanation of each bit:

¨ SIMEN A/B

The SIMEN A/B bit is the overall on/off control for

the SPI interface. When the SIMEN A/B bit is

cleared to zero to disable the SPI interface, the SDI,

SDO A/B, SCK A/B and SCS A/B lines will be in a

floating condition and the SPI operating current will

be reduced to <0.1

mA at 5V. When the bit is high the

SPI interface is enabled. Note that when the SIMEN

A/B bit changes from low to high the contents of the

SPI control registers will be in an unknown condition

and should therefore be initialised by the applica-

tion program.

¨ SIM0 A/B~SIM2 A/B

These three bits control the Master/Slave selection

and also setup the SPI interface clock speed when

in the Master Mode. The SPI clock is a function of

the system clock whether it be RC type or Crystal

type. If the Slave Mode is selected then the clock

will be supplied by the external Master device.

The following gives further explanation of each bit:

¨ TRF A/B

The TRF A/B bit is the Transmit/Receive Complete

flag and is cleared by the application program and

can be used to generate an interrupt. When the bit

is high the data has been transmitted or received. If

the bit is low the data is being transmitted or has not

yet been received.

¨ WCOL A/B

The WCOL A/B bit is used to detect if a data colli-

sion has occurred. If this bit is high it means that

data has been attempted to be written to the SMDR

A/B register during a data transfer operation. This

writing operation will be ignored if data is being

transferred. The bit can be cleared by the applica-

tion program. Note that using the CSEN A/B bit can

be disabled or enabled via configuration option.

¨ CSEN A/B

The CSEN A/B bit is used as an on/off control for the

SCS A/B pin. If this bit is low then the SCS A/B pin

will be disabled and placed into a floating condition.

If the bit is high the SCS A/B pin will be enabled and

used as a select pin.

¨ MLS A/B

The MLS A/B is used to select how the data is trans-

ferred, either MSB or LSB first. Setting the bit high

will select MSB first and low for LSB first.

Note that the SIMC2 A/B register is the same as the

SIMAR A/B register used by the I

2C interface.

· SPI Communication

After the SPI interface is enabled by setting the

SIMEN A/B bit high, then in the Master Mode, when

data is written to the SIMDR A/B register, transmis-

sion/reception will begin simultaneously. When the

data transfer is complete, the TRF A/B flag will be set

automatically. In the Slave Mode, when the clock sig-

nal from the master has been received, any data in the

SIMDR register will be transmitted and any data on

the SDI A/B pin will be shifted into the SIMDR A/B reg-

ister. The master should output an SCS A/B signal be-

fore a clock signal is provided and slave data transfers

should be enabled/disabled before/after an SCS A/B

signal is received.

HT83F02 Datasheet(PDF) 26 Page - Holtek Semiconductor Inc

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