HT83F02 datasheet(37/64 Pages) HOLTEK

37 / 64 page

HT83F02

Rev. 1.20

November 19, 2010

Timer Interrupt

For a timer generated interrupt to occur, the correspond-

ing timer interrupt enable bit must be first set. Each de-

vice contains two 8-bit timers whose corresponding

interrupt enable bits are known as ET0 and ET1and are

located in the INTC register. Each timer also has a cor-

responding timer interrupt request flag, which are

known as T0F and T1F, also located in the INTC regis-

ter. When the master interrupt and corresponding timer

interrupt enable bits are enabled, the stack is not full,

and when the corresponding timer overflows a subrou-

tine call to the corresponding timer interrupt vector will

occur. The corresponding Program Memory vector loca-

tions for Timer 0 and Timer1 are 08H and 0CH. After en-

tering the interrupt execution routine, the corresponding

interrupt request flags, T0F or T1F will be reset and the

EMI bit will be cleared to disable other interrupts.

Serial Interface Module - SIM - Interrupt

SIMA/B Interrupts include both the SPI and I

2C Inter-

rupts. The SIMA/B Mode is determined by the SIM2A/B,

SIM1A/B and SIM0A/B bits in the SIMC0A/B register.

For a SPI Interrupt to occur, the global interrupt enable

bit, EMI, and the corresponding SIMA/B interrupt enable

bit, ESII, must be first set. The SIMENA/B bit in the

SIMC0A/B register must also be set. An actual SPI In-

terrupt will take place when the flag, SIFA/B, is set, a sit-

uation that will occur when 8-bits of data are transferred

or received from either of the SPI interfaces. When the

interrupt is enabled, the stack is not full and an SIMA/B

interrupt occurs, a subroutine call to the SIMA/B inter-

rupt vector at location 10H, will take place. When the in-

terrupt is serviced, the SPIA/B interrupt request flag,

SIFA/B, will be automatically reset and the EMI bit will be

automatically cleared to disable other interrupts.

For an I

2C interrupt to occur, the corresponding interrupt

enable bit ESIIA/B must be first set. An actual I

2C inter-

rupt will be initialized when the SIMA/B interrupt request

flag, SIFA/B, is set, a situation that will occur when a

matching I

2C slave address is received or from the com-

pletion of an I

2C data byte transfer. When the interrupt is

enabled, the stack is not full and a SIMA/B interrupt oc-

curs, a subroutine call to the SIMA/B interrupt vector at

location 14H, will take place When an I

2C interrupt oc-

curs, the interrupt request flag SIFA/B will be reset and

the EMI bit will be cleared to disable other interrupts.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC or INTCH register until the corre-

sponding interrupt is serviced or until the request flag is

cleared by a software instruction.

It is recommended that programs do not use the

²CALL

subroutine

² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a

²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode. Only the

Program Counter is pushed onto the stack. If the con-

tents of the register or status register are altered by the

interrupt service program, which may corrupt the de-

sired control sequence, then the contents should be

saved in advance.

HT83F02 Datasheet(PDF) 37 Page - Holtek Semiconductor Inc

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