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HT68F13 Datasheet(PDF) 15 Page - Holtek Semiconductor Inc |
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HT68F13 Datasheet(HTML) 15 Page - Holtek Semiconductor Inc |
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15 / 161 page ![]() Symbol Parameter TestConditions Min. Typ. Max. Unit VDD Conditions fLIRC SystemClock(LIRC) 5V ¾ -10% 32 +10% kHz 2.2V~ 5.5V Ta= -40°C~+85°C -50% 32 +60% kHz fTIMER TimerInputPinFrequency ¾ ¾ ¾ ¾ 1 fSYS tRES ExternalResetLowPulseWidth ¾ ¾ 1 ¾ ¾ ms tINT InterruptPulseWidth ¾ ¾ 1 ¾ ¾ tSYS tLVR LowVoltageWidthtoReset ¾ ¾ 120 240 480 ms tLVD LowVoltageWidthtoInterrupt ¾ ¾ 20 45 90 ms tLVDS LVDO stabletime ¾ ¾ 15 ¾ ¾ ms tBGS VBG TurnonStableTime ¾ ¾ 200 ¾ ¾ ms tSST SystemStart-upTimerPeriod (Wake-upfromHALT) ¾ fSYS=HXT ¾ 1024 ¾ tSYS fSYS=ERC or HIRC ¾ 15~16 ¾ fSYS=LIRC OSC ¾ 1~2 ¾ Note: 1. tSYS=1/fSYS 2.*For fERC,astheresistortolerancewillinfluencethefrequencyaprecisionresistorisrecommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1 mF decoupling capacitor should be connectedbetween VDD and VSS andlocatedasclosetothedeviceaspossible. Power-onResetCharacteristics Ta=25 °C Symbol Parameter TestConditions Min. Typ. Max. Unit VDD Conditions VPOR VDD StartVoltagetoEnsure Power-onReset ¾ ¾ ¾ ¾ 100 mV RRVDD VDD RaisingRatetoEnsure Power-onReset ¾ ¾ 0.035 ¾ ¾ V/ms tPOR MinimumTimefor VDD Staysat VPOR toEnsurePower-onReset ¾ ¾ 1 ¾ ¾ ms HT68F13/HT68F14/HT68F15 EnhancedI/OFlashType MCU Rev.1.10 15 February9,2011 T i m e V D D V P O R R R V D D t P O R |
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